Events

Course Description: This introductory course will teach digital designers the basics of designing an FPGA-based solution. Using the latest Xilinx ISE development tools, students learn the basic FPGA development process of design entry, simulation, constraining, synthesis, implementation, timing analysis, and design download. Through a combination of lectures and hands-on labs, each step of the process will be explained and re-enforced through easy to follow step-by-step lab exercises.

Who Should Attend: Digital design engineers new to FPGA design and/or the Xilinx ISE tools.

Prerequisites: Digital design experience and general knowledge of FPGAs and HDLs (VHDL or Verilog) is required.

Course Description: This 1/2-day course will teach FPGA designers how to analyze design performance by using timing reports in order to achieve timing closure. Using the new Xilinx ISE 9.2 development tools, students will learn techniques for making path-specific timing constraints, creating timing groups and specifying external data and clock relationship for the timing on paths to and from the FPGA I/O pins by using the Xilinx Constraints Editor.

Who Should Attend: FPGA designers who want to improve a design’s speed and resource utilization.

Prerequisites: Familiarity with Xilinx FPGA design and the ISE tools.

Course Description: At power up, Xilinx FPGAs go through a configuration step, where their design identities are loaded into the FPGA SRAM. Recent advances in this area include the ability to configure from multiple design images stored in industry standard serial or parallel flash as well as configuring from on-chip flash memory. This 1/2-day course explains how to take advantage of these features, teaching the basic configuration techniques using serial and parallel flash. You will also look at some advanced options of running a multi-boot application with multiple design images. The concluding experiment of the day will show you how to take advantage of these features to design a fail-safe system capable of self-updating bitstreams over Ethernet.

Who Should Attend: Hardware engineers interested in taking advantage of advanced configuration techniques with Spartan-3A/3AN/3ADSP.

Prerequisites: Familiar with ISE Project Navigator (including iMPACT). Must know either VHDL or Verilog. Previous experience with Xilinx Platform Studio and MicroBlaze is helpful but not required.

Course Description: Designing a DDR2 memory system for an FPGA requires careful planning and special attention to system level details. This course covers the necessary elements for getting a working memory design running on the Xilinx Spartan-3A DSP Starter Board. You will explore the benefits of using theXilinx Memory Interface Generator (MIG), including an in-depth look at the back-end interface. We’ll also explain the essential details for board-level engineers to design their own boards, including the FPGA pinout, trace lengths, termination, and power. Learn how you can achieve first pass success with a proven design process.

Who should attend: FPGA and board-level hardware designers interested in learning about a complete, system-level FPGA/DDR2 interface.

Prerequisites: Familiar with ISE Project Navigator. Must know VHDL or Verilog

Course Description: The growth of FPGA-based embedded processors presents both opportunity and challenges for current FPGA designers. This half-day, hands-on workshop will teach you how to architect a MicroBlaze® based system using the latest Embedded Development Kit (EDK 9.2i) from Xilinx. Based on the Xilinx MicroBlaze v7.0 processor core, this class covers the details of defining your hardware system, implementing the design, incorporating application code, and booting. At the end of the course, students will take home sufficient knowledge to build and run their own MicroBlaze based systems.

Who Should Attend: FPGA designers interested using the MicroBlaze processor core in the Xilinx FPGAs.

Prerequisites: Knowledge of the Xilinx ISE implementation tools and general knowledge of microprocessors and embedded C programming.

Course Description: This 1/2-day course will teach FPGA designers how to analyze design performance by using timing reports in order to achieve timing closure. Using the new Xilinx ISE 9.2 development tools, students will learn techniques for making path-specific timing constraints, creating timing groups and specifying external data and clock relationship for the timing on paths to and from the FPGA I/O pins by using the Xilinx Constraints Editor.

Who Should Attend: FPGA designers who want to improve a design’s speed and resource utilization.

Prerequisites: Familiarity with Xilinx FPGA design and the ISE tools.

Course Description: Debugging is an integral part of any embedded systems development. FPGA-based embedded processors systems add the additional challenges of hardware that is just a malleable as the software and custom peripherals with limited visibility outside of the FPGA. Through a combination of lectures and hands-on labs this half-day, hands-on workshop will introduce the Xilinx Software Development Kit (SDK) software tools, the ChipScope Pro logic analyzer and the cross triggering capability between the two that can aid in debugging system or 'platform' level issues. Labs will take attendees through importing applications into the SDK and connecting to the GDB software debugger via JTAG interface to the processor Hardware Debug Module. ChipScope Pro Integrated Bus Analyzer (IBA) and Integrated Logic Analyzer (ILA) cores will be discussed and students will use the Xilinx Platform Studio (XPS) Debug Configuration Wizard to add the cores to a MicroBlaze embedded processor design. The combination of the SDK and ChipScope Pro tools will be used to debug the processor and custom peripherals and software.

Who Should Attend: Hardware and Software Engineers that will be developing and debugging FPGA embedded processor based systems.

Prerequisites: An understanding of embedded systems is required. Prior experience with the Xilinx EDK implementation tools is recommended.

Course Description: FPGA-based embedded processors present a new set of challenges and opportunities for embedded software developers. This half-day, hands-on workshop is specifically targeted to embedded software engineers who understand the basic concepts of embedded programming, but are unfamiliar with the FPGA-based embedded processor development flow. Through a combination of lectures and hands-on labs this course covers the Xilinx Embedded Development Kit (EDK) with the supporting applications, generating a board support package, software debugging, manipulating program memory space, and implementing a stand-alone boot sequence. The labs and lecture are based the MicroBlaze version 7 soft-core processor.

Who Should Attend: Embedded software engineers interested in FPGA-based embedded processing.

Prerequisites: Familiarity with general embedded software development and C programming. Experience with FPGA design tools is not required.

Course Description: Designers of processor-based networking systems need a solid understanding of the hardware and software components to determine how different combinations will affect overall performance. This full day hands-on session provides you with the practical knowledge necessary to use the Xilinx tools and IP to create a MicroBlaze based networking system within an FPGA.

Who Should Attend: Software and Hardware network system designers considering a TCP/IP processor based system.

Prerequisites: Introduction to Xilinx Embedded Software Development Tools, or prior experience with Xilinx Platform Studio (XPS) and the Software Development Kit (SDK).

Course Description: Are you interested in using Linux on your next Xilinx® MicroBlaze™ 7 design? Tired of trying to wade through the jumble of information in the open source world? Confused about whether or not you need an MMU? Then attend the new Avnet Speedway Workshop and we’ll show you all the things you need to know to get started with the 2.6 kernel, with or without the MMU.

Linux for MicroBlaze is centered around two new exciting developments from the embedded Linux GPL world and from Xilinx. Starting with the 2.6.13 kernel much of the work sponsored by the uClinux project was merged with the mainline Linux kernel, allowing kernel code based on the standard kernel.org source tree to be built for an MMU-less processor such as MicroBlaze 6 and earlier versions. Also, Xilinx has recently announced MicroBlaze 7, which allows the soft processor to be configured with an MMU as well. So now there are several possible combinations to consider, each with their own advantages and challenges.

This all-day introductory class will teach you the relationship between the flexible FPGA platform and the Linux operating system. We show you how to build the hardware from the ground up, using the Xilinx Spartan-3A™ DSP 1800A Starter Kit. Next, it’s all about getting the software files you need for development, configuring the kernel, and building and executing on the hardware platform. Your design includes a TCP/IP network, a web server and set up of your system to boot from power up using the open-source defacto standard U-Boot. With the Linux kernel in place, you can see how to add your own applications on top of the kernel, and how to debug them on the board over the network connection with GDB.

Who Should Attend: Software engineers and hardware engineers with software experience who need to upgrade their embedded system from a standalone software environment. If you need to run multiple concurrent applications and would benefit from features such as a TCP/IP protocol stack, comprehensive boot loader and a file system for RAM or ROM, then you should consider this course.

Prerequisites: This course is recommended for hardware and software developers interested in MicroBlaze processor development with Linux. Familiarity with the MicroBlaze soft-processor core and Xilinx Platform Studio™ is recommended. Prior attendance of the Introduction to EDK and MicroBlaze Part 1 and 2 SpeedWay is encouraged.

Course Description: Many signal processing applications require matrix inversion to solve a system of equations in real-time. This ½ day course will feature FPGA-based matrix operations in a variety of applications such as mobile WiMAX, automotive sonar, GPS, beamforming (medical and wireless), radar, and image processing. Hands on labs will use AccelDSP to leverage MATLAB, the native floating point simulation language, to explore hardware ramifications while implementing optimal fixed-point FPGA designs.

Who Should Attend: MATLAB algorithm designers and their FPGA hardware colleagues seeking the extra performance of Xilinx FPGAs.

Prerequisites: Knowledge of MATLAB. Familiarity with Xilinx FPGAs useful.

Course Description: System Generator for DSP is the industry’s leading high-level tool for designing high-performance DSP systems using Xilinx FPGAs. This 1/2-day, hands-on technical session will introduce the System Generator model-based abstractions that enable you to quickly develop high performance DSP systems, using system modeling and automatic code generation from Simulink® and MATLAB® (The MathWorks, Inc.). Key components include model creation using Simulink with highly optimized DSP blocks for Xilinx FPGAs, model simlution, hardware and sofware co-simulation, and finally integrating a custom System Generator design into a larger HDL-based project using the Xilinx ISE™ implementation tools.

Who Should Attend: Any Hardware or DSP system designer who needs to implement complex, high performance DSP algorithms in a Xilinx FPGA using intuitive, graphical-based design tools.

Prerequisites: Basic understanding of fundemental DSP concepts will be helpful. Prior experience with the Xilinx ISE™ implementation tools will also be useful.

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