Volatile FPGAs must load design-related configuration data from external memory at power-up. This presents a security hole that a cloner could exploit by copying bit-stream data and producing counterfeit designs.

1-Wire secure memories utilize an elegant challenge-and-response authentication sequence that enables FPGAs to differentiate between authorized and cloned environments. This determination either sets the system to normal operation or disables the design, thereby protecting the design investment from copying and cloning. The reference design supports the Spartan® 6/3A/3/2E and Virtex® E/2Pro/2 FPGA families.