CDCE62005RGZ - Clock Generator/Jitter Cleaner

The CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62005 achieves jitter performance well under 1 ps RMS10 kHz...20 MHz integration bandwidth.

It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS).

Key Features

Frequency synthesizer with PLL/VCO and partially integrated loop filter
Fully configurable outputs including frequency, output format, and output skew
Smart input multiplexer automatically switches between one of three reference inputs
Multiple operational modes include clock generation via crystal, SERDES startup mode, jitter cleaning, and oscillator holdover mode
Integrated EEPROM determines device configuration at power-up
Excellent jitter performance
Integrated frequency synthesizer including PLL, multiple VCOs, and loop filter:
- Full programmability facilitates phase noise performance optimization enabling jitter cleaner mode
- Programmable charge pump gain and loop filter settings
- Unique dual-VCO architecture supports a wide tuning range 1.750...2.356 GHz
Universal output blocks support up to 5 differential, 10 single-ended, or combinations of differential or single-ended:
- 0.35 ps RMS (10 kHz...20 MHz) output jitter performance
- Low output phase noise: -130 dBc/Hz at 1 MHz offset, Fc = 491.52 MHz
- Output frequency ranges from 4.25 MHz...1.175 GHz in synthesizer mode
- Output frequency up to 1.5 GHz in fan-out mode
- LVPECL, LVDS, LVCMOS, and special high output swing modes
- Independent output dividers support divide ratios from 1 - 80, non-continuous values supported
- Independent coarse skew control on all outputs, the coarse skew control does not operate for reference input frequencies less than 1 MHz
Flexible inputs with innovative smart multiplexer feature:
- Two universal differential inputs accept frequencies in the range of 40 kHz...1500 MHz (LVPECL), 800 MHz (LVDS), or 250 MHz (LVCMOS)