MPC8548E - PowerQUICC III Processor with 1.5 GHz

The MPC8548E networking/telecom processor features an embedded e500 core, targeting up to a 1.5 GHz core operation, an integrated security engine, 64-bit DDR/ DDR2 controller scaling up to 667 MHz data rate, dual 32-bit PCI or 64-bit PCI-X, 4-bit serial RapidIO® fabric technology and 4-bit PCI Express® (or single 8-bit PCI Express 1.0a), local bus I/O interfaces and four Gigabit Ethernet interfaces. The combination of these features makes this device an optimal communications processing solution for Ethernet-only or RapidIO interworking applications, such as enterprise networking, telecom transmission and switching and 3G wireless base stations.

The security engine includes Kasumi algorithm acceleration, making the MPC8548E an ideal choice for enhancing security protocol processing in 2.5G and 3G wireless network infrastructure. This device’s integrated security also includes XOR acceleration, which enhances system performance by offloading the computeintensive parity check in small-medium business enterprise and redundant array of inexpensive disk storage applications.

Features

Embedded e500 core, initial offerings up to 1.33 GHz, targeting up to 1.5 GHz
- Dual dispatch superscalar, seven-stage pipeline design with out-of-order issue and execution
- 3065 MIPS at 1333 MHz (estimated Dhrystone 2.1) ·· 36-bit physical addressing
Enhanced hardware and software debug support
Double-precision embedded scalar and vector floating-point APUs
Memory management unit (MMU)
Integrated L1/L2 cache:
- L1 cache—32 KB data and 32 KB instruction cache with line-locking support
- L2 cache—512 KB (8-way set associative); 512 KB/256 KB/128 KB/64 KB can be used as SRAM
- L1 and L2 hardware coherency
- L2 configurable as SRAM, cache and I/O transactions can be stashed into L2 cache regions
Integrated DDR memory controller with full ECC support, supporting:
- 200 MHz clock rate (400 MHz datarate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM
- 333 MHz clock rate (up to 667 MHzdata rate) DDR2 SDRAM
Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms
Four on-chip triple-speed Ethernetcontrollers (GMACs) supporting
10 and 100 Mbps, and 1 Gbps Ethernet/IEEE® 802.3 networks with MII, RMII, GMII, RGMII, RTBI and TBI physical interfaces:
- TCP/IP checksum acceleration
- Advanced QoS features
General-purpose I/O (GPIO)
Serial RapidIO and PCI Express high-speed interconnect interfaces, supporting:
- Single x8 PCI Express, or
- Single x4 PCI Express and single 4x serial RapidIO
On-chip network (OCeaN) switch fabric
Multiple PCI interface support:
- 64-bit PCI 2.2 bus controller (up to 66 MHz, 3.3V I/O)
- 64-bit PCI-X bus controller (up to 133 MHz, 3.3V I/O), or
- Flexibility to configure two 32-bit PCI controllers
166 MHz, 32-bit, 3.3 V I/O, local bus with memory controller
Integrated four-channel DMA controller
Dual I2C and Dual Universal Asynchronous Receiver/Transmitter (DUART) support
Programmable interrupt controller (PIC)
IEEE 1149.1 JTAG test access port
1.2 V core voltage with 3.3 V and 2.5 V I/O
783-pin FC-BGA package