Spartan-6 FPGA Connectivity Kit

The Spartan®-6 FPGA Connectivity kit is a complete, easy-to-use Connectivity Development and Demonstration platform for designing with standards based protocols – PCIe®, Ethernet, implementing low-cost protocol bridging, providing higher efficiency alternative to LVDS communication, etc in multiple market segments.

Provided with each Spartan-6 FPGA Connectivity Kit is a FULL seat of Production Netlist of Northwest Logic Packet DMA IP Core for implementing high speed and maintaining efficient data transfer on the PCIe link. This DMA IP Core can be targeted to any Xilinx Spartan-6 FPGA.

The Spartan-6 FPGA Connectivity Kit delivers a fully tested and supported Connectivity Targeted Reference Design that integrates built-in blocks for PCI Express and Memory Controller, soft IP for Gigabit Ethernet and the DMA IP core from Northwest Logic. The Targeted Reference Design is a framework that delivers – hardware design / RTL source Files, simulation environment, implementation scripts and design flows, software device drivers, an application and a GUI.

In addition, also included with each Spartan-6 FPGA Connectivity Kit is a full-seat of Xilinx ISE® Design Suite: Embedded Edition device locked to the Spartan-6 LX45T device.

Features

FPGA: XC6SLX45T FGG484-3CES Spartan-6

Serial Connectivity:

PCI Express x1 Edge Connector
SFP transceiver connector (SFP module not included)
SMA: 1 SMA port (Tx & Rx) for off-board GTP transceiver connectivity

Parallel Connectivity: 10/100/1000 Tri-Speed Ethernet

Memory:

DDR3 Component Memory 1Gb
16 MB Parallel (BPI) Flash (also available for configuration)
IIC 8 Kb IIC EEPROM

Additional Connectivity:

FMC-LPC connector (1 GTP Transceiver, 68 single-ended or 34 differential user defined signals)
User GPIO with two SMA connectors
4 User I/O (Digilent 2x6 Header)

Device Configuration:

Onboard JTAG configuration circuitry
128 MB Platform Flash XL
Quad SPI Flash 64 MB
16 MB Parallel (BPI) Flash
System ACE 2G Compact FLASH (CF) Card
JTAG

Clocking:

200 MHz Oscillator (Differential)
Oscillator socket (Single-Ended)
SMA Connectors for external clock (Differential)
Transceiver (GTP) Reference Clock port with 2 SMA connectors

Display & Control:

Video - DVI / VGA
16x2 LCD displays, LEDs
2X Push Buttons, 4X DIP

Power 12 V wall adapter or ATX

Voltage and current measurement capability of 2.5 V, 1.5 V, and 1.2 V, 1.0 V supplies

Kit Content

ROHS compliant SP605 Base Board including the XC6SLX45T-FGG484-3 FPGA

ISE® Design Suite: Embedded Edition (device-locked for the Spartan-6 LX45T FPGA):

Embedded Development Kit (EDK)
- Platform Studio (XPS)
- Software Development Kit (SDK) (Eclipse-IDE)
- MicroBlaze™ Soft Processor Core
ISE Design Suite: Logic Edition (Device-locked to Spartan-6 LX45T FPGA)
- ISE Foundation with Simulator (ISim)
- Xilinx CORE Generator™ System
- PlanAhead™ Design Analysis Tool
- ChipScope™ Pro and the ChipScope Pro Serial I/O Toolkit

Ecosystem OS/RTOS Support: Linux, uC/OS-II, Treck

Documentation:

Hardware Setup Guide
Getting Started Guide
Hardware Development Tutorial
Software Development Tutorial
MicroBlaze Processor Sub-System datasheet

Cables & Power:

Universal 12V power supply
Two USB cables – for JTAG download/debug and UART communication
One Ethernet cable – for host communication
One DVI-VGA adapter – standard interface for video display

Targeted Reference Design: MicroBlaze Processor Sub-System design that integrates the following key Embedded processing IP:

32-bit MicroBlaze Soft Processor
- Integrated Memory Management Unit (MMU)
- 16 KB Instruction & Data Caches
- JTAG Debug interface
- 100 MHz clock frequency
Memory:
- Multi-Port Memory Controller (MPMC) connected to 128 MB of 800 Mbps DDR3 memory
- Flash memory controllers connected to 32 Mbytes of NOR Flash memory
High-Performance I/O Peripherals:
- Gigabit Ethernet (Tri-Mode Ethernet MAC – TEMAC)
- UART 16550
- I2C, SPI – Serial Interface IP
- General Purpose Parallel I/O
Infrastructure IP
- Dual 32-bit Timers
- Interrupt Controller
- Bus infrastructure, Clock and Reset Management IP