The SPEAr1310 combines two ARM Cortex-A9 cores with a DDR3 (third-generation, double-data-rate) memory interface.

Together with ST’s low-power 55 nm HCMOS process technology, the SPEAr1310 delivers high computing power and customizability for a variety of embedded applications, with a high degree of cost competitiveness.

The dual processors support both fully symmetric and asymmetric operations, at speeds of 600 MHz (industrial worst-case conditions) for an equivalent of 3000 DMIPS.

The SPEAr1340 internal architecture is based on several shared subsystem logic blocks that are interconnected through a multilayer interconnection matrix (the BUSMATRIX).

The switch matrix structure enables different subsystem dataflows to be executed in parallel, which improves core platform efficiency.

SPEAr1310 datasheet

SPEAr1340 datasheet